This project has received funding from the EUís 7th FP for research, technological development and demonstration under grant agreement no 619871.

Publications

  1. Du, B. ; Sonza Reorda, M. ; Sterpone, L. ; Parra, L. ; Portela-Garcia, M. ; Lindoso, A. ; Entrena, L. A new solution to on-line detection of Control Flow Errors, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), DOI: 10.1109/IOLTS.2014.6873680, pp. 105 - 110.
  2. P. Bernardi, R. Cantoro, L. Ciganda, E. Sanchez, M. Sonza Reorda, S. De Luca, A. Sansonetti. On the in-field functional testing of decode units in pipelined RISC processors, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014.
  3. Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich. High Quality System Level Test and Diagnosis, IEEE Asian Test Symposium (ATS), 2014.
  4. Ubar, Raimund; Kostin, Sergei; Kruus, Helena; Aarna, Margit; Devadze, Sergei (2014). Environment for Analysis of Functional Self-Test Quality in Digital Systems. Proceedings of the Estonian Academy of Sciences. Technology, 2(63), 151 - 162. 
  5. Jasnetski, Artjom; Ubar, Raimund; Tsertov, Anton; Brik, Marina (2014). Software-based self-test generation for microprocessors with high-level decision diagrams. Proceedings of the Estonian Academy of Sciences, 63(1), 48 - 61.
  6. Kostin, Sergei; Ubar, Raimund; Mägi, Gunnar; Gorev, Maksim. (2014). Comparison of two approaches to improve functional BIST fault coverage. Proceedings of Baltic Electronics Conference – BEC, IEEE.
  7. Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan (2014). Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips. Proceedings of Baltic Electronics Conference – BEC, IEEE.
  8. Shibin, Konstantin; Jutman, Artur; Devadze, Sergei (2014). Asynchronous fault detection in IEEE P1687 instrument network. North Atlantic Test Workshop 2014.
  9. Ubar, Raimund; Tsertov, Anton; Jasnetski, Artjokm; Brik, Marina. (2014). Software-based Self-Test Generation for Microprocessors with High-Level Decision Diagrams. 15th IEEE Latin American Test Workshop - LATW, 12-15 March 2014
  10. Kostin, S.; Raik, J.; Ubar, R.; Jenihhin, M.; Vargas, F.; Bolzani Poehls, L.M.; Copetti, T.S., "Hierarchical identification of NBTI-critical gates in nanoscale logic," 15th IEEE Latin American Test Workshop - LATW, 12-15 March 2014
  11. F. Ghani Zadegan, E. Larsson, G. Carlsson. Robustness of TAP-based Scan Networks, International Test Conference, 2014.
  12. D. Nikolov, U. Ingelsson, V. Singh, E. Larsson. Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems, Microelectronics Reliability, Vol. 54, No. 5, pp. 1022-1049, 2014.
  13. J. Wan, H. Ebrahimi  and H.G. Kerkhoff, "The influence of No Fault Found  in Analogue CMOS Circuits", International Mixed-Signal, Systems and Sensors Workshop (IMS3TW), Porto Alegre Brazil, September 2014, pp. 3.1.1 - 3.1.6.
  14. F. Ghani Zadegan, E. Larsson, A. Jutman, S. Devadze, R. Krenz-Baath, “Design, Verification and Application of IEEE 1687”, in Proc. Asian Test Symposium (ATS’2014), Hangzhou, China, Nov.16-19, 2014.
  15. Gaudesi, M.; Jenihhin, M.; Raik, J.; Sanchez, E.; Squillero, G; Tihhomirov, V.; Ubar, R. “Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation”. EvoHOT: Bio-Inspired Heuristics for Design Automation, Granada, Spain, 23-25 April, 2014, pp. 1-12.
  16. Palermo, N.; Tihhomirov, V.; Copetti, T.S.; Jenihhin, M.; Raik, J.; Kostin, S.; Gaudesi, M.; Squillero, G.; Sonza Reorda, M.; Vargas, F.; Bolzani Poehls, L., "Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG", 2015 16th Latin-American Test Symposium (LATS), Pages: 1 - 6, DOI: 10.1109/LATW.2015.7102405 
  17. R. Cantoro, M. Sonza Reorda, A. Rohani, H.G. Kerkhoff, "On the Maximization of the Sustained Switching Activity in a Processor", 21st IEEE International On-Line Testing Symposium, July 2015, ISBN: 978-1-4799-0662-8 
  18. Riefert, A.; Cantoro, R.; Sauer, M.; Reorda, M.S.; Becker, B., "On the automatic generation of SBST test programs for in-field test", Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, Pages: 1186 - 1191 
  19. Du, B.; Sonza Reorda, M.; Sterpone, L.; Parra, L.; Portela-Garcia, M.; Lindoso, A.; Entrena, L., "On-line Test of Control Flow Errors: A new Debug Interface-based approach", IEEE Transactions on Computers,
    Year: 2015, Volume: PP, Issue: 99, Pages: 1 - 1, DOI: 10.1109/TC.2015.2456014 
  20. Perez Acle J., Cantoro R., Sanchez E., Sonza Reorda M., "On the Functional Test of the Cache Coherency Logic in Multi-core Systems", 6th IEEE Latin American Symposium on Circuits and Systems, LASCAS, Montevideo - Uruguay, February 2015 
  21. Gaudesi, M.; Reorda, M.Sonza; Pomeranz, I., "On test program compaction", 2015 20th IEEE European Test Symposium (ETS), Pages: 1 - 6, DOI: 10.1109/ETS.2015.7138771 
  22. Perez Acle J., Cantoro R., A.T. Hailemichael, Sanchez E., Sonza Reorda M., "Observability solutions for in-field functional test of processor-based systems", 2015 IEEE Conference on Design of Circuits and Integrated Systems (DCIS), November 2015 
  23. NTF2014, Malmö, November 26th 2014, " NFF – No Fault Found, How to know what is unknown", ASTER Technologies, Christophe LOTZ
  24. 1st International RAFES Workshop – May 28-29 2015 - Cluj-Napoca, Romania, " Board NFF – No Fault Found – Between dream and reality - First results from BASTION case studies", ASTER Technologies, Christophe LOTZ
  25. Larsson, Erik; Eklow, Bill; Davidsson, Scott; Aitken, Rob; Jutman, Artur; Lotz, Christophe, "No Fault Found: The root cause,” VLSI Test Symposium (VTS), 2015 IEEE 33rd , vol., no., pp.1,1, 27-29 April 2015. doi: 10.1109/VTS.2015.7116284
  26. René Krenz-Baath, Farrokh Ghani Zadegan, Erik Larsson "Access Time Minimization in IEEE 1687 Networks”, International Test Conference, 2015.
  27. D. Nikolov, E. Larsson: Optimizing the Level of Confidence for Multiple Jobs. IEEE Transactions on Computers, 2015. 
  28. R. Cantoro, M. Sonza Reorda, A. Rohani and H.G. Kerkhoff, "On the Maximization of the Sustained Switching Activity in a Processor", in Proc. IEEE International On-Line testing Workshop (IOLTW), Greece, July 2015.
  29. H.G. Kerkhoff and H. Ebrahimi, "Intermittent Resistive Faults in Digital CMOS Circuits", in Proc. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, April 2015. (Best Paper Award)
  30. H.G. Kerkhoff and H. Ebrahimi, "Detection of Intermittent Resistive Faults in Electronic Systems based on the Mixed-Signal Boundary-Scan Standard", in Proc. Asia Symposium on Quality Electronic Design (asQED), Kuala Lumpur Malaysia, August 2015. 
  31. Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein. A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. IEEE Euromicro Digital Systems Design (DSD) Conference, Madeira, Portugal, 2015.
  32. Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Vineeth Govind, Thomas Hollstein, Gert Jervan. A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers. Network on Chip Symposium (NOCS), Vancouver, Canada, 2015.
  33. Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein. Automated Minimization of Concurrent Online Checkers for Network-on-Chips. 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015), 29.6. - 1.7.2015, Bremen - Germany.
  34. I. Aleksejev, A. Jutman, S. Devadze, K. Shibin, “Virtual Reconfigurable Scan-chains on FPGAs for Optimized Board Test” in Proc. 16th IEEE Latin-American Test Symposium (LATS’2015), Puerto Vallarta, Mexico, March 25 - 27, 2015, pp. 1-6.
  35. Jasnetski, Artjom; Raik, Jaan; Tsertov, Anton; Ubar, Raimund (2015). New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS. Belgrade, Serbia, April 22-24, 2015: IEEE Computer Society Press, 1-6.
  36. Palermo, N.; Tihhomirov, V.; Copetti, T.S.; Jenihhin, M.; Raik, J.; Kostin, S.; Gaudesi, M.; Squillero, G.; Sonza Reorda, M.; Vargas, F.; Bolzani Poehls, L. (2015). Rejuvenation of Nanoscale Logic at NBTI-Critical Paths Using Evolutionary TPG. In: 16th IEEE Latin-American Test Symposium March 25 - 27, 2015, Puerto Vallarta, Mexico (1-6). IEEE Computer Society Press.
  37. Jutman, Artur; Lotz, Christophe; Larsson, Erik; Sonza Reorda, Matteo; Jenihhin, Maksim; Raik, Jaan; Kerkhoff, Hans; Krenz-Baath, Rene; Engelke, Piet. (2017). BASTION: Board and SoC Test Instrumentation for Ageing and No Failure Found. Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, 2017: Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, 2017. 
  38. Vain, Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Kaur, Apneet; Jenihhin, Maksim; Raik, Jaan (2017). Multi-fragment Markov model guided online test generation for MPSoC. ICT in Education, Research and Industrial Applications : Integration, Harmonization and Knowledge Transfer : Proceedings of the 13th International Conference, ICTERI 2017, Kyiv, Ukraine, May, 2017. Ed. Ermolayev, V. et al. Aachen: RWTH Aachen University, 594-607. (CEUR Workshop Proceedings; 1844)
  39. Vain, Jüri; Kaur, Apneet; Tsiopoulos, Leonidas; Raik, Jaan; Jenihhin, Maksim (2017). Modeling for multi-view interference analysis of design aspects in MPSoC designs. Proceedings of 22nd IEEE European Test Symposium : RESCUE 2017, Workshop on Reliability, Security and Quality, May 25-26, 2017, Limassol, Cyprus. KIOS Research Center | University of Cyprus, 1-6
  40. Jenihhin, Maksim; Squillero, Giovanni; Copetti, Thiago Santos; Tihhomirov, Valentin; Kostin, Sergei; Gaudesi, Marco; Vargas, Fabian; Raik, Jaan; Sonza Reorda, Matteo; Bolzani Poehls, Leticia; Ubar, Raimund; Medeiros, Guilherme Cardoso (2016). Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. Journal of Electronic Testing-Theory and Applications, 273-289, 10.1007/s10836-016-5589-x.
  41. Karputkin, Anton; Raik, Jaan (2016). A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage. In: ACM/IEEE Design, Automation & Test in Europe Conference (DATE) (1-4). IEEE Computer Society.
  42. Osimiry, E.; Kostin, S.; Raik, J.; Ubar, R. (2016). A Tool for Random Test Generation Targeting High Diagnostic Resolution. In: 15th Biennial Baltic Electronics Conference (1-4). ieee: IEEE Computer Society Press.
  43. Copetti, Thiago; Medeiros, Guilherme; Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund. (2016). Gate-Level Modelling of NBTI-Induced Delays Under Process Variations. 17th IEEE Latin-American Test Symposium (LATS 2016), Foz do Iguaçu, Brazil, 6th - 8th April 2016. IEEE Computer Society Press, 75-80.
  44. Pellerey, F.; Jenihhin, M.; Squillero, G.; Raik, J.; Sonza Reorda, M.; Tihhomirov, V.; Ubar, R. (2016). Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. The 25th Asian Test Symposium (ATS), Hiroshima, November 21-24, 2016.. IEEE, 304-309.
  45. Cantoro, R.; Sonza Reorda, M.; Rohani, A.; Kerkhoff, H.G. (2015), On the Maximization of the Sustained Switching Activity in a Processor. In: 21st IEEE International On-Line Testing Symposium, Elia, Halkidiki, Greece, July 2015. pp. 34-35
  46. Cantoro, R.; Montazeri, M.; Reorda, M. Sonza; Zadegan, F. Ghani; Larsson, E. (2016), On the diagnostic analysis of IEEE 1687 networks. In: 2016 21th IEEE European Test Symposium (ETS)
  47. Cantoro, Riccardo; Montazeri, Mehrdad; Sonza Reorda, Matteo; Ghani Zadegan, Farrokh; Larsson, Erik (2015), On the Testability of IEEE 1687 Networks. In: 24th IEEE Asian Test Symposium, Mumbai (IN), November 22-25, 2015. pp. 211-216.
  48. Cantoro, R.; Montazeri, M.; Sonza Reorda, M.; Zadegan, F. Ghani; Larsson, E. (2016), Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks. In: 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 4-6 July 2016. pp. 167-172
  49. Cantoro, Riccardo; Palena, Marco; Pasini, Paolo; Sonza Reorda, Matteo (2016), Test Time Minimization in Reconfigurable Scan Networks. In: 2016 IEEE 25th Asian Test Symposium (ATS), Hiroshima (JP), November 21-24, 2016
  50. Tšertov, Anton; Jutman, Artur; Devadze, Sergei; Sonza Reorda, Matteo; Larsson, Erik; Ghani Zadegan, Farrokh; Cantoro, Riccardo; Montazeri, Mehrdad; Krenz-Baath, Rene (2016), A Suite of IEEE 1687 Benchmark Networks. In: 2016 IEEE International Test Conference (ITC), Fort Worth, TX (USA), November 15-17, 2016.
  51. Riefert, Andreas; Cantoro, Riccardo; Sauer, Matthias; Sonza Reorda, Matteo; Becker, Bernd (2016), A Flexible Framework for the Automatic Generation of SBST Programs. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Volume: 24, Issue: 10, Oct. 2016 pp. 3055 - 3066, ISSN 1063-8210.
  52. Riefert, Andreas; Cantoro, Riccardo; Sauer, Matthias; Reorda, Matteo Sonza; Becker, Bernd (2016), Effective generation and evaluation of diagnostic SBST programs. In: 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas (USA), 25-27 April 2016
  53. Marco Gaudesi; Irith Pomeranz; Matteo Sonza Reorda; Giovanni Squillero “New Techniques to Reduce the Execution Time of Functional Test Programs” IEEE Transactions on Computers, Year: 2017, Volume: 66, Issue: 7, Pages: 1268 - 1273.
  54. Du, B.; Sanchez, E.; Reorda, M. Sonza; Acle, J. Perez; Tsertov, A. (2016), FPGA-controlled PCBA power-on self-test using processor's debug features. In: 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016.
  55. Perez Acle, Julio; Cantoro, Riccardo; Hailemichael, Abel Teklu; Sanchez, Ernesto; Sonza Reorda, Matteo (2015), Observability solutions for in-field functional test of processor-based systems. In: XXX Conference on Design of Circuits and Integrated Systems (DCIS), Estoril (PT), November 25-27, 2015.
  56. Perez Acle, Julio; Cantoro, Riccardo; Sanchez, Ernesto; Sonza Reorda, Matteo; Squillero, Giovanni (2016), Observability solutions for in-field functional test of processor-based systems: a survey and quantitative test case evaluation. In: MICROPROCESSORS AND MICROSYSTEMS. - ISSN 0141-9331.
  57. An, G.; Cantoro, R.; Sanchez, E.; Reorda, M. Sonza (2017), On the detection of board delay faults through the execution of functional programs. In: 2017 18th IEEE Latin American Test Symposium (LATS), Bogota (CO), 13-15 March 2017
  58. S. Odintsov, A. Jutman, S. Devadze, "Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus" Proc of 48th IEEE International Test Conference (ITC’2017), Fort Worth, TX, USA, Oct 31 - Nov 2, 2017.
  59. Hans G Kerkhoff, Hassan Ebrahimi, "Detection of intermittent resistive faults in electronic systems based on the mixed-signal boundary-scan standard", 6th Asia Symposium on Quality Electronic Design (ASQED), pp. 77-82, August 2015.
  60. Hans G Kerkhoff, Hassan Ebrahimi, "Investigation of Intermittent Resistive Faults in Digital CMOS Circuits," Journal of Circuits, Systems and Computers (JCSC), 25(3), pp. 1640023, March 2016.
  61. Hassan Ebrahimi, Hans G Kerkhoff, "Testing for Intermittent Resistive Faults in CMOS Integrated Systems," Euromicro Conference on Digital System Design (DSD), pp. 703-707, August 2016.
  62. Alireza Rohani, Hassan Ebrahimi, Hans G Kerkhoff, "A software framework to calculate local temperatures in CMOS processors," 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 183-188, September 2016.
  63. Hassan Ebrahimi, Alireza Rohani, Hans G Kerkhoff, "Detecting intermittent resistive faults in digital CMOS circuits," IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 87-90, September 2016. (Best paper Award)
  64. Hassan Ebrahimi, Hans G Kerkhoff,"Reusing Intermittent Resistance Fault Monitor to Detect Board-level faults" Submitted in IEEE Transactions on Emerging Topics in Computing (TETC), March 2017.
  65. A. Jutman, “Filling a Gap in Board-Level At-Speed Test Coverage” in Proc. IEEE Int. Workshop on Defects, Adaptive Test, Yield and Data Analysis (DATA’2015), Anaheim, CA, USA, Oct 8-9, 2015, pp. 1-7.
  66. I. Aleksejev, S. Devadze, A. Jutman, “On Coverage of Timing Related Faults at Board Level” in Proc. IEEE 21st European Test Symposium (ETS’2016), Amsterdam, Netherlands, May 24-27, 2016, pp. 1-2.
  67. I. Aleksejev, S. Devadze, A. Jutman, K. Shibin, “Optimization of Boundary Scan Tests using FPGA-based Efficient Scan Architectures”, in Journal of Electronic Testing: Theory and Applications (JETTA), Springer, June 2016, Vol. 32, No. 3, pp. 245-255.
  68. I. Aleksejev, A. Jutman, S. Devadze, “Run-Time Reconfigurable Instruments for Advanced Board-Level Testing”, in Proc. of AUTOTESTCON’2016, Anaheim, USA, Sept 12-15, 2016, pp. 385-392.
  69. A. Jutman, S. Devadze, K. Shibin, “Synchronization, Calibration and Triggering of IEEE 1687 Embedded Instruments”, in Proc. of the 17th Workshop on RTL and High Level Testing (WRTLT’2016), Nov. 24-25, 2016, Hiroshima, Japan, pp. 1-6.
  70. I. Aleksejev, A. Jutman, S. Devadze, “Run-Time Reconfigurable Instruments for Advanced Board-Level Testing” in IEEE Instrumentation and Measurement Magazine, Vol 20, No. 4, 2017.
  71. K. Shibin, S. Devadze, A. Jutman, “On-line Fault Classification and Handling in IEEE1687 based Fault Management System for Complex SoCs” in Proc. 17th IEEE Latin-American Test Symposium (LATS’2016), Foz do Iguaçu, Brazil, April 6-8, 2016, pp. 69-74.
  72. A. Jutman, K. Shibin, S. Devadze, “Reliable Health Monitoring and Fault Management Infrastructure based on Embedded Instrumentation and IEEE 1687,” in Proc. of AUTOTESTCON’2016, Anaheim, USA, Sept 12-15, 2016, pp. 240-249.
  73. S. Odintsov, A. Jutman, S. Devadze, I. Aleksejev, "Embedded Instrumentation Toolbox for Screening Marginal Defects and Outliers for Production", in Proc. of AUTOTESTCON’2017, Schaumburg, USA, Sept 11-14, 2017, pp. TBD. (accepted for publication).
  74. M. Beck and P. Engelke, "On Safety and Security Aspects of IEEE 1687 Networks," in International Test Standards Application Workshop (TESTA), 2016.
  75. C. Laudert, “Challenges in hierarchical test and monitoring”, Nordic Test Forum, 2014.
  76. K. Petersen, D. Nikolov, U. Ingelsson, G. Carlsson, F. Ghani Zadegan, and E. Larsson, “Fault injection and fault handling: an MPSoC demonstrator using IEEE P1687”, International On-Line Testing Symposium (IOLTS), 2014.
  77. F. Ghani Zadegan, R. Krenz-Baath, and E. Larsson, “Upper-bound computation for optimal retargeting in IEEE 1687 networks”, International Test Conference (ITC), 2016.
  78. Dimitar Nikolov & Erik Larsson, Clustered checkpointing: Maximizing the level of confidence for non-equidistant checkpointing, Integration, the VLSI Journal,  2016.
  79. Dimitar Nikolov & Erik Larsson, Maximizing level of confidence for non-equidistant Checkpointing, Asia and South Pacific Design Automation Conference, ASP-DAC 2016. 
  80. E. Larsson and F. Ghani Zadegan, “Accessing on-chip instruments through the life-time of systems”, Latin-American Test Symposium (LATS), 2016.
  81. F. Ghani Zadegan, D. Nikolov, and E. Larsson, “In-field system-health monitoring based on IEEE 1687”, System-on-Chip Conference (SoCC), 2016.

 

International Patent

·        P. Bogner, A. Kalt, J. Mejri, M. Pernull, „Built-in self-test for ADC“ (WO2017005748), Jan. 12, 2017

 

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